Integrated circuits often use zener diodes to form reference voltages or high power clamp diodes. The diodes must be stable with little or no drift to ensure the stable operation of the integrated circuit which uses the diode. Zener diodes with breakdown regions at or near the surface of the integrated circuit are generally very unstable and exhibit many other undesirable characteristics.
Several attempts have been made at providing zener diodes with buried or subsurface breakdown regions to avoid unstable diode operation. These attempts, however, have been met with little or limited success due to a wide variety of reasons.
For example, U.S. Pat. No. 4,079,402 produces a breakdown region which is so shallow, that unstable diode performance is exhibited.
U.S. Pat. No. 4,213,806 exhibits an additional problem in that when conventional bi-polar processing techniques disclosed in this patent are applied to wafer scale substrates, there is a tendency for the buried zener diode to break down at the surface of the silicon wafer and thus become non-buried, with a corresponding potential for unstable performance.
Although U.S. Pat. Nos. 4,771,011 and 4,601,760 disclose forming a buried zener diode in a wafer scale integrated circuit, the processes involved are much different and include many additional steps added to the conventional bipolar process, which unduly complicate and add to the processing time required to produce a finished zener diode. Further, forming additional devices on the large scale wafer involve the use of additional masks and thus, mask registration and alignment problems present additional difficulties.